1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device having grooves filled with a semiconductor filler.
2. Description of the Related Art
FIG. 36(a) is a plan view for use in illustration of the diffusion structure of a conventional MOSFET 101, and FIG. 36(b) is an enlarged view of the part encircled by the chain-dotted line in the FIG. 36(a). The gate insulating film 151 is omitted from FIG. 36(a) and the gate insulating film 51 as described below is also omitted from FIG. 1 and FIG. 31.
The MOSFET 101 has a growth layer 112 of an n-type epitaxial layer, and about in the center of the rectangular region of the growth layer 112 for the single MOSFET 101, there is a p-type base region 133 formed by impurity diffusion.
A plurality of elongated active grooves 122a are provided in parallel to one another across the base region 133. An n-type source region 139 is formed by impurity diffusion in the base region 133 and on one or both sides of each active groove 122a. Two source regions 139 oppose each other between the active grooves 122a, and a p+-type ohmic region 138 is formed by impurity diffusion between these two source regions 139.
A plurality of rectangular ring-shaped, guard grooves 122b with a narrow width are provided concentrically around the active grooves 122a and the base region 133. In other words, the active grooves 122a and the base region 133 are concentrically surrounded by these guard grooves 122b. 
FIGS. 37(a) and 37(b) are sectional views taken along the lines I—I and II—II, respectively in FIG. 36(a).
At the inner circumferential surface and the bottom of the active groove 122a, a gate insulating film 151 is formed. The region surrounded by the gate insulating film 151 is filled with a gate electrode 158 made of a polysilicon material.
Here, the gate insulating film 151 is not formed at the inner circumference of the guard groove 122b, a p-type silicon single crystal is epitaxially grown from the bottom and side face of the guard groove 122b, and the guard grooves 122b are filled with a guard region 123 made of the silicon single crystal.
An oxide film 157 is provided on the gate electrodes 158 and the guard regions 123. The oxide film 157 is patterned to have an opening each on the source region 139 and the ohmic region 138. The surfaces of the source regions 139 and the ohmic regions 138 are exposed at the bottom surfaces of the openings.
A source electrode 161 made of a thin metal film is formed on the surfaces of the exposed regions and the surface of the oxide film 157.
The growth layer 112 is provided on one surface of a substrate 111 of an n+-type silicon single crystal, and a drain electrode 171 of a thin metal film is formed on the other surface of the substrate 111.
The base region 133 is in contact with the gate insulating film 151 in a position lower than the source region 139. When the contacted portion is made to serve as an inversion region, the source electrode 161 is connected to a ground potential and positive voltage is applied to the drain electrode 171, the application of positive voltage not less than the threshold voltage to the gate electrode 158 inverts the inversion region of the base region 133 to be n-type conductivity. The inversion layer connects the source region 139 and the growth layer 112 to allow current to flow.
In this state, when the voltage of the gate electrode 158 is less than threshold voltage, the inversion layer disappears and the current does not flow. For example, the voltage can be less than threshold voltage to connect the gate electrode 158 to the source electrode 161.
In this state, the pn junction between the base region 133 and the growth layer 112 is reverse-biased, and a depletion layer expands both inside the base region 133 and the growth layer 112.
These ring-shaped semiconductor regions that have the same conductivity as that of the base region and concentrically surround the base region are generally called “guard rings” and the guard region 123 serves as a guard ring in the MOSFET 101. Once the depletion layer transversely expanding in the growth layer 112 reaches the guard region 123, the depletion layer expands outwardly from the guard region 123. The depletion layer sequentially reaches the concentric guard regions 123 and expands, and therefore the depletion layer is more expanded than the case without the guard regions 123. The electric field intensity in the growth layer 112 is reduced accordingly.
Herein, if {100} includes all the following plane orientations:                (100), (010), (001), ({overscore (1)}00), (0{overscore (1)}0), (00{overscore (1)})the surface plane orientation of the substrate 111 is {100}, and the plane orientation of the surface of the growth layer 112 grown on the surface of the substrate 111 or the bottom surface of the guard grooves 122b is also {100}.        
The substrate 111 has, for example, a mark (orientation flat) that indicates the {100} direction of the surface of the substrate 111.
In order to form a patterned resist film for the guard grooves 122b so that the guard grooves 122b are formed by etching, the pattern extending direction of the guard grooves 122b and the mark of the substrate 111 are aligned, and in this way, the pattern for the guard grooves 122b extends in the {100} direction.
The side faces of the guard grooves 122b are formed perpendicularly to the surface of the substrate 111, and the side faces are parallel to each other or orthogonal to each other. Therefore, a {100} plane is exposed at the inner circumferential side face of the guard grooves 122b that are actually formed by etching.
At the bottom face, a {100}-orientated plane the same as the surface of growth layer 112 is exposed, and therefore the {100} plane is exposed at the bottom and all the side faces inside the guard grooves 122b. 
Consequently, the silicon single crystal forming the guard regions 123 uniformly grows to fully fill the guard grooves 122b. 
In this case, when the four sides of the guard grooves 122b are connected at right angles, a part curved at right angles forms at the surface of the pn junction formed between the guard region 123 and the growth layer 112, which lowers the withstanding voltage.
Therefore, according to the conventional techniques, in order to prevent the withstanding voltage from being lowered, the four corners of the guard groove 122b are curved at a predetermined radius of curvature, so that the surface part of the pn junction formed at the interface between the guard region 123 and the growth layer 112 is not curved at right angles.
However, when the guard grooves 122b are rounded at the four corners like this, as shown in FIG. 36(b), the side face S1 in the part of the guard groove 122b extending linearly in the direction horizontally in the figure and the side face S2 extending linearly in the direction from the top to the bottom of the figure are in the {100} orientation but the round part connecting side faces S1 and S2 is not in the {100} plane orientation. For example, the intermediate side face S3 is in the {110} plane orientation.
The growth rate of the silicon single crystal to form the guard region 123 is different between the linear part and the curved part at the four corners of the guard grooves 122b. This prevents the guard grooves 122b from being uniformly filled inside. Voids left in the unevenly filled guard regions 123 can lower the withstanding voltage in the position, which makes the device defective as a whole.